Astute Approach to Handling Memory Layouts of Regular Data Structures
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216208%3A11320%2F23%3A10448342" target="_blank" >RIV/00216208:11320/23:10448342 - isvavai.cz</a>
Result on the web
<a href="https://rdcu.be/c3gP9" target="_blank" >https://rdcu.be/c3gP9</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/978-3-031-22677-9_27" target="_blank" >10.1007/978-3-031-22677-9_27</a>
Alternative languages
Result language
angličtina
Original language name
Astute Approach to Handling Memory Layouts of Regular Data Structures
Original language description
Programmers of high-performance applications face manychallenging aspects of contemporary hardware architectures. One of thecritical aspects is the efficiency of memory operations which is affectednot only by the hardware parameters such as memory throughput orcache latency but also by the data-access patterns, which may influencethe utilization of the hardware, such as re-usability of the cached dataor coalesced data transactions. Therefore, a performance of an algorithmcan be highly affected by the layout of its data structures or the orderof data processing which may translate into a more or less optimal se-quence of memory operations. These effects are even more pronouncedon highly-parallel platforms, such as GPUs, which often employ specificexecution models (lock-step) or memory models (shared memory).In this work, we propose a modern, astute approach for managing andimplementing memory layouts with first-class structures that is veryefficient and straightforward. This approach was implemented in Noarr,a GPU-ready portable C++ library that utilizes generic programming,functional design, and compile-time computations to allow the program-mer to specify and compose data structure layouts declaratively whileminimizing the indexing and coding overhead. We describe the mainprinciples on code examples and present a performance evaluation thatverifies our claims regarding its efficiency.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach<br>I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2023
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Algorithms and Architectures for Parallel Processing
ISBN
978-3-031-22677-9
ISSN
0302-9743
e-ISSN
1611-3349
Number of pages
22
Pages from-to
507-528
Publisher name
Springer
Place of publication
Berlin
Event location
Copenhagen, Denmark
Event date
Oct 10, 2022
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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