Verification of COMBO6 VHDL Design

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216224%3A14330%2F03%3A00008325" target="_blank" >RIV/00216224:14330/03:00008325 - isvavai.cz</a>

Alternative codes found

RIV/63839172:_____/03:00000009

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Verification of COMBO6 VHDL Design

Original language description

This technical report presents current results and experiences of the formal verification of VHDL design of Combo6 hardware accelerator card. Information about formal verification itself is enriched by description of transformation from VHDL to the Cadence SMV specification language and the system of assertions established as a compact way of communication with VHDL designers.

Czech name

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Czech description

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Type

A - Audiovisual production

CEP classification

IN - Informatics

OECD FORD branch

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Project

<a href="/en/project/GA201%2F03%2F0509" target="_blank" >GA201/03/0509: Automated Verification of Parallel and Distributed Systems</a><br>

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2003

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

ISBN

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Place of publication

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Publisher/client name

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Version

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Carrier ID

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