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Parallelization of brute-force attack on MD5 hash algorithm on FPGA

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216224%3A14330%2F19%3A00115599" target="_blank" >RIV/00216224:14330/19:00115599 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/VLSID.2019.00034" target="_blank" >http://dx.doi.org/10.1109/VLSID.2019.00034</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/VLSID.2019.00034" target="_blank" >10.1109/VLSID.2019.00034</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Parallelization of brute-force attack on MD5 hash algorithm on FPGA

  • Original language description

    FPGA implementation of MD5 hash algorithm is faster than its software counterpart, but a pre-image brute-force attack on MD5 hash still needs 2 power 128 iterations theoretically. This work attempts to improve the speed of the brute-force attack on the MD5 algorithm using hardware implementation. A full 64-stage pipelining is done for MD5 hash generation and three architectures are presented for guess password generation. A 32/34/26-instance parallelization of MD5 hash generator and password generator pair is done to search for a password that was hashed using the MD5 algorithm. The total performance of about 6G trials/second has been achieved using a single Virtex-7 FPGA device.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Result continuities

  • Project

  • Continuities

    I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Others

  • Publication year

    2019

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    32nd International Conference on VLSI Design, VLSID 2019

  • ISBN

    9781728104096

  • ISSN

    1063-9667

  • e-ISSN

    2380-6923

  • Number of pages

    6

  • Pages from-to

    88-93

  • Publisher name

    IEEE

  • Place of publication

    New York

  • Event location

    New York

  • Event date

    Jan 1, 2019

  • Type of event by nationality

    CST - Celostátní akce

  • UT code for WoS article

    000470061200016