Design of a Low Power and Area Efficient Bfloat16 based Generalized Systolic Array for DNN Applications

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216275%3A25530%2F22%3A39919612" target="_blank" >RIV/00216275:25530/22:39919612 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/9764899" target="_blank" >https://ieeexplore.ieee.org/document/9764899</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/RADIOELEKTRONIKA54537.2022.9764899" target="_blank" >10.1109/RADIOELEKTRONIKA54537.2022.9764899</a>

Result language
angličtina
Original language name
Design of a Low Power and Area Efficient Bfloat16 based Generalized Systolic Array for DNN Applications
Original language description
Nowadays demand for artificial intelligence (AI) enabled mobile platforms is increasing. From healthcare services to defense and from remote to urban area, there is a huge demand of secured and power efficient devices. The performance of these platforms can be enhanced by providing an efficient compute engine. These compute engines perform a huge amount of matrix operations. The most popular choice for large matrix computation is a systolic array. In general, the systolic array performance degrades for the large input matrices, due to the trade off between resource utilization and computation delay. To address this issue, we need a systolic array with a control unit to re-configure the array according to the requirement of the computation. Computation array can be further improved by handling the negative weights and reduce the MAC operations. In this paper, we proposed a generalized bfloat16 based systolic array in which the sign of the partial sum (PS) is predicted before computation. The PS sign aids in network pruning which enhances system performance. The proposed system is implemented on a Virtex-7 FPGA board and it performs 2.21 similar to and 4.19x better in terms of area and power compared to single-precision based systolic array.
Czech name
—
Czech description
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Project
<a href="/en/project/LTAIN19100" target="_blank" >LTAIN19100: Smart contactless technology development for smart fencing</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2022
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2022 32ND INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA)
ISBN
978-1-72818-686-3
ISSN
—
e-ISSN
—
Number of pages
5
Pages from-to
44-48
Publisher name
IEEE
Place of publication
NEW YORK
Event location
Kosice
Event date
Apr 21, 2022
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
000856002200011

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