Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26210%2F13%3APU108434" target="_blank" >RIV/00216305:26210/13:PU108434 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1007/978-3-319-02294-9_84" target="_blank" >http://dx.doi.org/10.1007/978-3-319-02294-9_84</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/978-3-319-02294-9_84" target="_blank" >10.1007/978-3-319-02294-9_84</a>
Alternative languages
Result language
angličtina
Original language name
Hardware in the Loop Simulation Model of BLDC Motor Taking Advantage of FPGA and CPU Simultaneous Implementation
Original language description
This paper presents Hardware in the Loop (HIL) simulation of the BLDC motor used in aerospace applications. Due to a high frequency driving signals and a high dynamics of the electrical part of the BLDC motor, the utilization of FPGA is necessary. The algorithm is distributed between the CPU and the FPGA and targeted to dSPACE modular hardware.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
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Continuities
R - Projekt Ramcoveho programu EK
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Mechatronics 2013: Recent Technological and Scientific Advances
ISBN
978-3-319-02293-2
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
135-142
Publisher name
Springer International Publishing
Place of publication
Cham, Heidelberg, New York, Dordrecht, London
Event location
Brno
Event date
Oct 7, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000345341700018