Specification and Synthesis of Reusable Modules in VHDL

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F01%3APU28646" target="_blank" >RIV/00216305:26220/01:PU28646 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Specification and Synthesis of Reusable Modules in VHDL
Original language description
Hardware-Software codesign, which implements a given specification with a set of system components such as ASIC, FPGA, CPLD, and processors, includes several key tasks such as system component allocation, functional partitioning, quality metrics estimation, and design space exploration. Hardware synthesis of embedded cores is one of the hardware-software codesign steps. In this paper, we focus on hardware reusable module specification. In addition, we describe how we can get many implementations to thespecified reusable module using design space exploration during high-level synthesis (HLS) process. We propose a reusable module specification figure, and identify main concepts of the component created by the proposed methodology.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formal approaches in digital circuit diagnostics - testable design verification</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2001
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of fourth International Wokshop on IEEE Design and Diagnostics of Electronic Circuits and Systems IEEE DDCSE01
ISBN
963-7175-16-4
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
137-140
Publisher name
SZIF-UNIVERSITAS Ltd., Hungary
Place of publication
Gyor, Hungary
Event location
Gyor
Event date
Apr 18, 2001
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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