Scaling in Analog Circuit Design

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F02%3APU29204" target="_blank" >RIV/00216305:26220/02:PU29204 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

Scaling in Analog Circuit Design

Original language description

The impact of scaling on the analog performance of CMOS circuits was studied. The solution space for analog scaling was explored between two dimensions: "a standard digital scaling" axis and an "increased bandwidth and dynamic-range" axis. Circuit simulation was applied to explore trends in noise and linearity performance under analog operating conditions at device level and for a basic circuit block. It appears that a single scaling rule is not applicable in the analog circuit domain.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2002

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

ELECTRONIC DEVICES AND SYSTEMS 02 - PROCEEDINGS

ISBN

80-214-2180-0

ISSN

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e-ISSN

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Number of pages

4

Pages from-to

150-153

Publisher name

Vysoké učení technické v Brně

Place of publication

Brno

Event location

Brno

Event date

Sep 9, 2002

Type of event by nationality

EUR - Evropská akce

UT code for WoS article

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