Approximate Symbolic Analysis of Real Circuits
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F02%3APU29610" target="_blank" >RIV/00216305:26220/02:PU29610 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Approximate Symbolic Analysis of Real Circuits
Original language description
Enhanced method for approximate symbolic analysis that assures validity of approximated expressions over a certain interval of network parameters.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2002
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of Telecommunication and Signal Processing TSP-2002
ISBN
80-214-2172-X
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
98-101
Publisher name
FEKT VUT Brno
Place of publication
Brno
Event location
Brno
Event date
Sep 4, 2002
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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