Automatic Generation of Design Equations
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F05%3APU51575" target="_blank" >RIV/00216305:26220/05:PU51575 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
Automatic Generation of Design Equations
Original language description
The paper deals with a method for automatic generation of simplified DC mathematical model of a nonlinear analog circuit for the purpose of modeling and circuit design. The method presented is based on approach that has been successfully used for linearcircuits [2]. It simplifies circuit equations by means of simplifying KVL and KCL relations and nonlinear device models.
Czech name
Automatické generování návrhových rovnic
Czech description
Článek pojednává o automatickém generování návrhových rovnic pro nelineární obvody.
Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
—
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proc. of Electronic Devices and Systems Conference (EDS'2005)
ISBN
80-214-2990-9
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
381-384
Publisher name
Brno University of Technology
Place of publication
Brno
Event location
Brno
Event date
Sep 15, 2005
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
—