A Novel Background Calibration in 10-bit, 40 MHz, 54 mW Pipelined ADC Using Switched-capacitor Approach

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F05%3APU52685" target="_blank" >RIV/00216305:26220/05:PU52685 - isvavai.cz</a>

Result on the web

—

DOI - Digital Object Identifier

—

Result language

angličtina

Original language name

A Novel Background Calibration in 10-bit, 40 MHz, 54 mW Pipelined ADC Using Switched-capacitor Approach

Original language description

The article describes a new background calibration technique, which is used in new 10-bit low power pipelined ADC. The switched-capacitor approach (SC) is utilized in proposed ADC as well. The low power consumption is one of the most important issues considered in the design, because the ADC is intended for using in portable applications. Well-known operational-amplifier (op-amp) sharing technique was modified and used to decrease the power usage. The capacitor scaling approach is suitable for the samepurpose. The basic problems coupled to SC such as clock feedthrough from digital part through the switches, capacitor mismatch and op-amp non-idealities have been taken into account in design of the ADC. These error sources are canceled or roughly attenuated by means of novel background calibration or using known analog-domain techniques. The special op-amps and comparators were designed for this purpose. The power consumption of the op-amps was taken into account too.

Czech name

Nová postkalibrační metoda v řetězovém převodníku AD pracujícím v technice SC

Czech description

The article describes a new background calibration technique, which is used in new 10-bit low power pipelined ADC. The switched-capacitor approach (SC) is utilized in proposed ADC as well. The low power consumption is one of the most important issues considered in the design, because the ADC is intended for using in portable applications. Well-known operational-amplifier (op-amp) sharing technique was modified and used to decrease the power usage. The capacitor scaling approach is suitable for the samepurpose. The basic problems coupled to SC such as clock feedthrough from digital part through the switches, capacitor mismatch and op-amp non-idealities have been taken into account in design of the ADC. These error sources are canceled or roughly attenuated by means of novel background calibration or using known analog-domain techniques. The special op-amps and comparators were designed for this purpose. The power consumption of the op-amps was taken into account too.

Type

D - Article in proceedings

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

—

Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2005

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Seminář o řešení projektu GA ČR 102/03/H105, Moderní metody řešení, návrhu

ISBN

80-214-3089-3

ISSN

—

e-ISSN

—

Number of pages

9

Pages from-to

47-55

Publisher name

UREL Brno

Place of publication

Brno

Event location

Brno

Event date

Oct 24, 2005

Type of event by nationality

CST - Celostátní akce

UT code for WoS article

—