Topology Transformations for Symbolic Analysis
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F06%3APU58494" target="_blank" >RIV/00216305:26220/06:PU58494 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Topology Transformations for Symbolic Analysis
Original language description
This paper deals with circuit topology transformations for approximate symbolic analysis of linearized circuits. The method is based on two-graph approach. The structure of current and voltage graphs is modified in order to decrease the number of commonspanning trees, i.e. the number of symbolic terms.
Czech name
Topologická transformace pro symbolickou analýzu
Czech description
Článek pojednává o topologické transformaci pro symbolickou analýzu.
Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proc. of the 2006 IEEE Int?l Midwest Symposium on Circuits and Systems [CD-ROM]
ISBN
1-4244-0173-9
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
200-204
Publisher name
IEEE
Place of publication
Puerto Rico, USA
Event location
San Juan
Event date
Aug 6, 2006
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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