BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F06%3APU58990" target="_blank" >RIV/00216305:26220/06:PU58990 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE
Original language description
This article describes the implementation of a RocketIO bit-error rate tester (BERT) on the DSP custom board FD64x. The BER test is aimed at the serial link between two transceivers placed in the Virtex-II Pro FPGA. The tester module generating PRBS pattern, verifying received data and counting bit errors.
Czech name
BIT ERROR RATE TESTER založený na stukturách FPGA
Czech description
Článek popisuje implementaci RocketIO bit-error testeru v FPGA sysému.
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
—
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003
ISBN
80-214-3130-
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
433-436
Publisher name
VUT Brno
Place of publication
Brno
Event location
Brno
Event date
Feb 14, 2006
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—