BER Evaluation Embedded Module for Serial Links
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F06%3APU62351" target="_blank" >RIV/00216305:26220/06:PU62351 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
BER Evaluation Embedded Module for Serial Links
Original language description
The paper describes an embedded tester of Bit Error Rate (BER) in serial links based on the Spartan-3 FPGA device. The tester is suitable for long-term test without need of a human intervence. All management and measured data evaluation is done in a remote computer that is connected to the tester via Ethernet interface.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2006
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
International Conference on Signals and Electronic Systems, conference proceedings
ISBN
83-921172-4-7
ISSN
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e-ISSN
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Number of pages
3
Pages from-to
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Publisher name
Institute of Circuit Theory, Metrology and Materials Science of the Technical University of Lodz, Poland
Place of publication
Lodž
Event location
Lodz, Poland
Event date
Sep 17, 2006
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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