Multi-Core Computing Unit for Artificial Neural Networks in FPGA Chip
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F09%3APU81136" target="_blank" >RIV/00216305:26220/09:PU81136 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Multi-Core Computing Unit for Artificial Neural Networks in FPGA Chip
Original language description
The paper describes multi-core computing unit implemented into FPGA chip. The unit is used for accelerating of Artificial Neural Networks computations.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F08%2F1116" target="_blank" >GA102/08/1116: Methods of Signal Digitizing for Advanced Sensors</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
ICINCO 2009 6th International Conference on Informatics in Control, Automationa and Robotics Proceedings Volume 1 - Inteligent Control Systems and Optimization
ISBN
978-989-8111-99-9
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
INSTICC PRESS
Place of publication
Portugal
Event location
Milano
Event date
Jul 2, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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