Efficient FPGA Implementation of Linear Interpolation
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F10%3APU88147" target="_blank" >RIV/00216305:26220/10:PU88147 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Efficient FPGA Implementation of Linear Interpolation
Original language description
The paper focuses on hardware implementation of fast linear interpolation into FPGA chip.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F08%2F1116" target="_blank" >GA102/08/1116: Methods of Signal Digitizing for Advanced Sensors</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Electronic Devices and Systems IMAPS CS International Conference 2010 Proceedings
ISBN
978-80-214-4138-5
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
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Publisher name
Vysoké učení technické v Brně, Antonínská 548/1
Place of publication
Brno
Event location
Brno
Event date
Sep 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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