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Determining Effective Testability Degree of Analog Circuits

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F12%3APU98582" target="_blank" >RIV/00216305:26220/12:PU98582 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Determining Effective Testability Degree of Analog Circuits

  • Original language description

    The paper deals with the parametric fault diagnosis of linear analog circuits in the frequency domain. The testability degree, which is referred to as the total number of testable network parameters, is theoretically independent of nominal values of network parameters, the set of test frequencies and the fault detection method. However, practical results show that the effective testability determined numerically using the Singular Value Decomposition of sensitivity matrix (Jacobian) depends on the normalization of network parameters, frequency response measurement methods and a selected set of test frequencies. The differences between the theoretical and the practical testability degree will be discussed on a practical example of RC phase shifter filter.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JA - Electronics and optoelectronics

  • OECD FORD branch

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2012

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems

  • ISBN

    978-1-4577-2092-5

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    427-430

  • Publisher name

    Technical University of Lodz

  • Place of publication

    Warsaw

  • Event location

    Varšava

  • Event date

    May 24, 2012

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article