A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F12%3APU99544" target="_blank" >RIV/00216305:26220/12:PU99544 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
A 12-bit second order sigma-delta modulator design in 0.7 um CMOS technology
Original language description
The presented work deals with design of the sigma-delta modulator in CMOS I2100 0,7 um technology. This modulator is designed using the switched capacitor technique (SC). For offset compensation of operational amplifiers (opamps) each integrator uses correlated double sampling technique (CDS), which minimize impact of offset of opamps. The sigma-delta modulator is part of the system for signal processing from sensor applications. Requirements for this converter were resolution 12-bits, voltage range 4 V, common mode voltage 2,5 V, +- 2 V input signal amplitude, bandwidth of a processed signal 5 kHz. Second order structure CIDIDF (Cascaded Integrator with Distributed Input and Distributed Feedback) was chosen.
Czech name
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Czech description
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Project
<a href="/en/project/GAP102%2F11%2F1379" target="_blank" >GAP102/11/1379: Novel Intelligent Submicron Structures and Microsystems for Advanced Microsensors</a><br>
Continuities
S - Specificky vyzkum na vysokych skolach

Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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