FPGA Based 1 Gbps Ethernet Header Detector

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F12%3APU99568" target="_blank" >RIV/00216305:26220/12:PU99568 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

FPGA Based 1 Gbps Ethernet Header Detector

Original language description

This paper presents a study about a hardware implementation of the Ethernet header detector implemented in FPGA circuits. The header detector is able to detect the TCP/IP and UDP/IP header contents for both the IPv4 and the IPv6 protocols. This hardwareimplementation allows access to the headers content faster than the software implementation. Therefore, it is suitable for many different high-speed Ethernet devices.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

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Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2012

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of the conference Vsacký Cáb 2012

ISBN

978-80-214-4579-6

ISSN

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e-ISSN

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Number of pages

4

Pages from-to

1-4

Publisher name

Neuveden

Place of publication

Neuveden

Event location

Vsetín

Event date

Aug 29, 2012

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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