Simulation and Implementation of LDPC Code in FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F13%3APU103364" target="_blank" >RIV/00216305:26220/13:PU103364 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Simulation and Implementation of LDPC Code in FPGA
Original language description
The paper deals with implementation of Low-Density Parity-Check (LDPC) codes [1] in FPGA-based bridge for Free-Space Optical link.The coder was designed with a regular parity matrix for code rate 1/2. The matrix of dimension 8x16 for the experimental implementation was found using a random search in MATLAB. The main advantage of this matrix is the decoder can correct all single-bit errors. The simulation for all possible values shows that Bit Error Ratio (BER) is zero. This result was not obtained withother matrices. An experimental communication channel was realized with encoder and decoder implemented in FPGA Virtex 5 development board ML505. DIP switches are sources for information bits and these values are shown on LCD display. The bit-flipping method is used in decoder and result code word is shown in the second line on the LCD display.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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