Area Efficient Implementation of Fast Fourier Transform for ASIC

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F14%3APU109454" target="_blank" >RIV/00216305:26220/14:PU109454 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/7296365" target="_blank" >https://ieeexplore.ieee.org/document/7296365</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TSP.2015.7296365" target="_blank" >10.1109/TSP.2015.7296365</a>

Result language
angličtina
Original language name
Area Efficient Implementation of Fast Fourier Transform for ASIC
Original language description
The paper presents an architecture of a module for computation of a Discrete Fourier Transform with a Fast Fourier Transform algorithm. The architecture is optimized for low area implementation and is suitable for implementation in application specific integrated circuits (ASIC). Software in C++ was written for automatic FFT module generation with various parameters. The software generates fully synthesizable VHDL code and SystemVerilog testbench for verification.
Czech name
—
Czech description
—

Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
37th International Conference on Telecommunications and Signal Processing (TSP)
ISBN
978-80-214-4983-1
ISSN
—
e-ISSN
—
Number of pages
3
Pages from-to
753-755
Publisher name
Asszisztencia Szervezó Kft.
Place of publication
Budapest, Hungary
Event location
Berlín
Event date
Jul 1, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000375231000256

Similar results(10)