Processor Model for the Instruction Mapping Tool
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F16%3APU118516" target="_blank" >RIV/00216305:26220/16:PU118516 - isvavai.cz</a>
Result on the web
<a href="http://www.nesus.eu/proceedings" target="_blank" >http://www.nesus.eu/proceedings</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Processor Model for the Instruction Mapping Tool
Original language description
This paper describes the model designed for the instruction mapping tool, which can be used for generating the low level assembly code for the digital signal processing algorithms. The model is based on the Very Long Instruction Word architecture. The Texas Instrument TMS320C6678 was the pattern and finally was described with the created model. The paper is showing the parameters of the hardware resources and also the instruction set.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/LD15034" target="_blank" >LD15034: Systems for Effective Hardware Modeling and Software Mapping</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the First PhD Symposium on Sustainable Ultrascale Computing Systems (NESUS PhD 2016)
ISBN
978-84-608-6309-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
41-44
Publisher name
University Carlos III of Madrid
Place of publication
Madrid
Event location
Timisoara, Romania
Event date
Feb 8, 2016
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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