Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F16%3APU120115" target="_blank" >RIV/00216305:26220/16:PU120115 - isvavai.cz</a>
Result on the web
<a href="http://www.sciencedirect.com/science/article/pii/S2405896316327136" target="_blank" >http://www.sciencedirect.com/science/article/pii/S2405896316327136</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1016/j.ifacol.2016.12.075" target="_blank" >10.1016/j.ifacol.2016.12.075</a>

Result language
angličtina
Original language name
Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays
Original language description
This article deals with encryption on Field Programmable Gate Array (FPGA). The first part describes current state of symmetric and asymmetric cryptography. The following part focuses on the AES algorithm and its implementation in VHDL language. The last part shows testing results of mentioned implementation on card NFB-40G2 containing FPGA from Xilinx series Virtex-7.
Czech name
—
Czech description
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Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture

Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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