Zero Cross Detection Using Phase Locked Loop
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F16%3APU120576" target="_blank" >RIV/00216305:26220/16:PU120576 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1016/j.ifacol.2016.12.050" target="_blank" >http://dx.doi.org/10.1016/j.ifacol.2016.12.050</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1016/j.ifacol.2016.12.050" target="_blank" >10.1016/j.ifacol.2016.12.050</a>
Alternative languages
Result language
angličtina
Original language name
Zero Cross Detection Using Phase Locked Loop
Original language description
This paper discusses zero cross detection method for the time synchronization purpose that is based on phase locked loop. After familiarizing with PLL concept and its blocks, example design of the PLL is realized. Simulation schema is introduced to examine and analyse PLL behaviour under different grid interferences. Performed tests show two potential issues multiple zero crossing in the zero cross area may cause instability of the loop and the presence of harmonics may cause shifts of the zero cross event.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
14th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2016
ISBN
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ISSN
2405-8963
e-ISSN
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Number of pages
5
Pages from-to
464-468
Publisher name
Neuveden
Place of publication
Brno/Lednice
Event location
Brno/Lednice
Event date
Oct 5, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000401255800050