The Optimisation of Large Scale Logical Circuits

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F19%3APU131930" target="_blank" >RIV/00216305:26220/19:PU131930 - isvavai.cz</a>
Result on the web
<a href="http://www.feec.vutbr.cz/conf/EEICT/archiv/sborniky/EEICT_2019_sbornik.pdf" target="_blank" >http://www.feec.vutbr.cz/conf/EEICT/archiv/sborniky/EEICT_2019_sbornik.pdf</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
The Optimisation of Large Scale Logical Circuits
Original language description
In the phase of designing the logical circuits, it is essential to minimise the number of elements because it leads to the more reliable, more secure, and cheaper solution. For the logical functions with less than 4 variables, the Karnaugh maps are suitable. However, in practice, we encounter usually a much more complex function, in those cases, we could apply Boolean algebra laws directly or use the Quine-McCluskey method, which is based on their systematic use. Unfortunately, this method does not usually provide a minimal form of logical function for really large scale logical functions, and in a result may be redundant expressions. For that reason, we show that we could apply an additional phase which leads to the set covering problem which needs to cover all the inputs by the obtained outputs. Since this problem is NP-hard, it is necessary to use heuristic methods, such as simulated annealing.
Czech name
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Czech description
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Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 25th Conference STUDENT EEICT 2019
ISBN
978-80-214-5735-5
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
469-473
Publisher name
Neuveden
Place of publication
Brno
Event location
Brno
Event date
Apr 27, 2017
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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