Hardware cryptographic module for FPGA with dynamic hash functions routing

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F19%3APU133247" target="_blank" >RIV/00216305:26220/19:PU133247 - isvavai.cz</a>
Result on the web
<a href="https://www.radio.feec.vutbr.cz/ieee/userfiles/downloads/archive/2019-Mikulov/sbornik.pdf" target="_blank" >https://www.radio.feec.vutbr.cz/ieee/userfiles/downloads/archive/2019-Mikulov/sbornik.pdf</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Hardware cryptographic module for FPGA with dynamic hash functions routing
Original language description
This paper deals with design of hardware cryptographic module for System-on-Chip that can be simulated on FPGA. The main function of this module is dynamic routing of SHA-3 hash function candidates that are commonly used s X11 hash algorithm. Proposed design was verified and evaluated using Virtual Platform methodology and aims to be an example of development of system based on Virtual Platform. Designed architecture can be deployed on FPGA or real hardware platform. This hardware can be used in Internet-of-Things or another related applications.
Czech name
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Czech description
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Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of IEEE Student Branch Conference Mikulov 2019
ISBN
978-80-214-5781-2
ISSN
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e-ISSN
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Number of pages
53
Pages from-to
39-41
Publisher name
Neuveden
Place of publication
Vysoké učení technické v Brně Fakulta elektrotec
Event location
Mikulov, Czech republic
Event date
Sep 9, 2019
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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