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Current–Mode Fractional–Order Electronically Controllable Integrator Design

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F20%3APU137290" target="_blank" >RIV/00216305:26220/20:PU137290 - isvavai.cz</a>

  • Result on the web

    <a href="https://ieeexplore.ieee.org/document/9294923" target="_blank" >https://ieeexplore.ieee.org/document/9294923</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/ICECS49266.2020.9294923" target="_blank" >10.1109/ICECS49266.2020.9294923</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Current–Mode Fractional–Order Electronically Controllable Integrator Design

  • Original language description

    This contribution presents a design of a current–mode fractional–order electronically controllable integrator which can be used as a building block for a design of fractional–order (FO) circuits. The design is based on a 2nd–order Follow–the–Leader–Feedback topology which is suitably approximated to operate as an integrator of a fractional order. The topology is based on Operational Transconductance Amplifiers (OTAs), Adjustable Current Amplifiers (ACAs) and Current Follower (CF). The proposed structure offers the ability of the electronic control of its fractional order and also the electronic control of the frequency band. Simulations in Cadence IC6 (spectre) and more importantly experimental measurements were carried out to support the proposal. If wider bandwidth where the approximation is valid is required, a higher order structure must be used as also shown in this paper by utilization of a 4th–order FLF topology.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20201 - Electrical and electronic engineering

Result continuities

  • Project

    <a href="/en/project/LTC18022" target="_blank" >LTC18022: Analogue fractional systems, their synthesis and analysis</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2020

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 2020 IEEE International Conference on Electronics Circuits and Systems (ICECS)

  • ISBN

    978-1-7281-6044-3

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    1-4

  • Publisher name

    IEEE

  • Place of publication

    Glasgow, Scotland

  • Event location

    Glasgow, Scotland

  • Event date

    Nov 23, 2020

  • Type of event by nationality

    CST - Celostátní akce

  • UT code for WoS article

    000612696300139