On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU145341" target="_blank" >RIV/00216305:26220/22:PU145341 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21240/22:00359271
Result on the web
<a href="https://dl.acm.org/doi/abs/10.1145/3538969.3544423" target="_blank" >https://dl.acm.org/doi/abs/10.1145/3538969.3544423</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1145/3538969.3544423" target="_blank" >10.1145/3538969.3544423</a>

Result language
angličtina
Original language name
On Secure and Side-Channel Resistant Hardware Implementations of Post-Quantum Cryptography
Original language description
Currently, many post-quantum cryptography schemes have been implemented on various hardware platforms in order to provide efficient solutions in cybersecurity services. As researchers and hardware developers focus primarily on designs providing small latency and requiring fewer hardware resources, their implementations could seldom omit protection techniques against various physical attacks. This paper studies potential attacks on the cryptography implementations that run on Field-Programmable Gate Array (FPGA) platforms. We mainly analyze how Post-Quantum Cryptography (PQC) implementations could be vulnerable on various platforms. Further, we aim at the FPGA-based implementations of National Institute of Standards and Technology (NIST)’s PQC competition finalists. Our study should present to developers the current overview of attacks and countermeasures that can be implemented on specific PQC schemes on FPGA platforms. Moreover, we present novel implementation of one universal countermeasure component and reveal additional resources that are needed.
Czech name
—
Czech description
—

Project
<a href="/en/project/VJ02010010" target="_blank" >VJ02010010: Tools for AI-enhanced Security Verification of Cryptographic Devices</a><br>
Continuities
S - Specificky vyzkum na vysokych skolach

Publication year
2022
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
ARES '22: Proceedings of the 17th International Conference on Availability, Reliability and Security
ISBN
978-1-4503-9670-7
ISSN
—
e-ISSN
—
Number of pages
9
Pages from-to
1-9
Publisher name
ACM
Place of publication
Vienna, Austria
Event location
Vídeň
Event date
Aug 23, 2022
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—

Similar results(10)