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A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-mu m CMOS

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F22%3APU145801" target="_blank" >RIV/00216305:26220/22:PU145801 - isvavai.cz</a>

  • Alternative codes found

    RIV/68407700:21460/22:00360604

  • Result on the web

    <a href="https://ieeexplore.ieee.org/document/9894730" target="_blank" >https://ieeexplore.ieee.org/document/9894730</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/TVLSI.2022.3203148" target="_blank" >10.1109/TVLSI.2022.3203148</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-mu m CMOS

  • Original language description

    This article presents the experimental results for a multiple-input operational transconductance amplifier (MI-OTA). To achieve extended linearity under 0.5-V low voltage supply, the circuit employs three linearization techniques: the bulk-driven (BD), the source degeneration, and the input voltage attenuation created by the MI metal-oxide-semiconductor transistor technique (MI-MOST). Although the linearization techniques result in reduced dc gain, the self-cascode transistors are used to boost the gain of the MI-OTA. Furthermore, the MI-MOST simplifies the internal structure of the OTA and may reduce the complexity of the applications. The MI-OTA operates in the subthreshold region and offers tunability by a bias current in the nanoampere range. The circuit is capable to work with 0.5-V supply voltage while consuming 24.77 nW. The circuit was fabricated using the 0.18- mu m Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology and it occupies a 0.01153-mm(2) silicon area. Intensive simulation and experimental results confirm the benefits and robustness of the design.

  • Czech name

  • Czech description

Classification

  • Type

    J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database

  • CEP classification

  • OECD FORD branch

    20200 - Electrical engineering, Electronic engineering, Information engineering

Result continuities

  • Project

  • Continuities

    S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2022

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Name of the periodical

    IEEE Trans. on VLSI Systems.

  • ISSN

    1063-8210

  • e-ISSN

    1557-9999

  • Volume of the periodical

    30

  • Issue of the periodical within the volume

    11

  • Country of publishing house

    US - UNITED STATES

  • Number of pages

    9

  • Pages from-to

    1739-1747

  • UT code for WoS article

    000857343700001

  • EID of the result in the Scopus database

    2-s2.0-85139389731