Influence and Algorithmic Suppression of Parasitic Capacitance of the R-C-NR Layer Contacts in Thick-Film Fractional-Order Capacitor
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F24%3APU151247" target="_blank" >RIV/00216305:26220/24:PU151247 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/SoutheastCon52093.2024.10500259" target="_blank" >http://dx.doi.org/10.1109/SoutheastCon52093.2024.10500259</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/SoutheastCon52093.2024.10500259" target="_blank" >10.1109/SoutheastCon52093.2024.10500259</a>
Alternative languages
Result language
angličtina
Original language name
Influence and Algorithmic Suppression of Parasitic Capacitance of the R-C-NR Layer Contacts in Thick-Film Fractional-Order Capacitor
Original language description
The realization of capacitive fractional-order circuit elements based on distributed layer R-C-NR (resistive, capacitive, resistive) structures is analyzed for implementation in thick-film technology. The metal contacts for layer connections are found to introduce parasitic capacitance which is modeled in this work treating the contacts as lumped-element capacitors. A design method for the algorithmic suppression of the parasitic capacitance is presented. The design method uses a genetic algorithm to optimize the interconnections and parameters of the R-C-NR structures that comprise the circuit to counteract the effects of the parasitic capacitance. Using modified nodal analysis, the impact of the parasitic capacitance on the admittance characteristics is simulated and suppressed by the algorithm. Simulations validate this method, with best performance for fractional orders between 0 and 0.5, where it is possible to design circuits with a frequency range of constant admittance phase of 2.5 to 4 decades with a maximum admittance phase deviation of 2 degrees.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
<a href="/en/project/GA23-06070S" target="_blank" >GA23-06070S: Fundamental research on designing of CMOS fractional-order elements</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of IEEE SoutheastCon 2024 Conference
ISBN
979-8-3503-1710-7
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
1235-1242
Publisher name
IEEE
Place of publication
Atlanta, GA, USA
Event location
Atlanta, Georgia
Event date
Mar 15, 2024
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
001219464000202