Low-latency AES encryption for High-Frequency Trading on FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F24%3APU151250" target="_blank" >RIV/00216305:26220/24:PU151250 - isvavai.cz</a>
Result on the web
<a href="https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdf" target="_blank" >https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdf</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Low-latency AES encryption for High-Frequency Trading on FPGA
Original language description
This paper presents a Field Programmable Gate Array (FPGA) powered low--latency solution for secure communication with the stock exchange. It presents architecture design and optimization techniques used to ensure the required security level without impacting the latency, which is the most critical domain in High-Frequency Trading (HFT). The National Stock Exchange of India (NSE) chose Advanced Encryption Standard (AES) with 256 bit key length in Galoise-Counter Mode (GCM) as the encryption algorithm for Non-NEAT Front End (NNF) connections.
Czech name
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Czech description
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Project
<a href="/en/project/VI20162018036" target="_blank" >VI20162018036: Cryptographic privacy protection in 100GbE networks</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings I of the 30th Conference STUDENT EEICT 2024: General papers
ISBN
978-80-214-6231-1
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
236-240
Publisher name
Brno University of Technology, Faculty of Electronic Engineering and Communication
Place of publication
neuveden
Event location
Brno
Event date
Apr 23, 2024
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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