Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals from Sensors

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F24%3APU151753" target="_blank" >RIV/00216305:26220/24:PU151753 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/10648767" target="_blank" >https://ieeexplore.ieee.org/document/10648767</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TIM.2024.3427752" target="_blank" >10.1109/TIM.2024.3427752</a>

Result language
angličtina
Original language name
Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals from Sensors
Original language description
Phase-Locked Loops (PLLs) are versatile electronic circuits that, among others, are used in various sensor applications (e.g., medical) for their ability to generate stable and precise clock signals. This paper introduces a novel PLL-based frequency demodulation system designed for processing very slow signals, ranging from a few Hz to several hundreds of Hz, with amplitudes in the order of several hundreds of millivolts. The system incorporates specialized analog multipliers tailored for essential PLL components, including the voltage-controlled oscillator, phase detector, loop filter with variable DC offset, and base-band filter, all optimized for the purpose of frequency demodulation. These multipliers were fabricated using the TSMC 0.18 µm, 1.8 V CMOS process. The primary design objectives are simplicity, reduced complexity, low power consumption (merely 15 mW), and versatility for applications in sensing engineering. To validate the functionality of the proposed PLL system under practical conditions, we present an example of electrocardiogram signal demodulation, demonstrating its operational performance.
Czech name
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Czech description
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Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering

Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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