Emulation of Fractional-Order Impedance with α=0.5 using MOSFET Revised RC-Ladder Topology

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F24%3APU151913" target="_blank" >RIV/00216305:26220/24:PU151913 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/SOUTHEASTCON52093.2024.10500247" target="_blank" >http://dx.doi.org/10.1109/SOUTHEASTCON52093.2024.10500247</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/SOUTHEASTCON52093.2024.10500247" target="_blank" >10.1109/SOUTHEASTCON52093.2024.10500247</a>

Result language
angličtina
Original language name
Emulation of Fractional-Order Impedance with α=0.5 using MOSFET Revised RC-Ladder Topology
Original language description
Approximations of fractional-order capacitors are widely implemented using passive RC ladder topologies. One alternative to this approach is to replace resistors in these topologies with MOSFET devices biased to operate as resistors. To validate this approach, fractional-order capacitors with alpha = 0.5 are approximated (with a +/- 1 degrees phase error target) with MOSFET revised ladder topologies in parallel and series configurations. The measured phases of these realized approximations had average differences of 0.7 degrees and 3.1 degrees for the parallel and series cases, respectively, with maximum differences of 1.7 degrees and 13.3 degrees for the frequency band from 100 Hz to 10 kHz.
Czech name
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Czech description
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Project
<a href="/en/project/GA23-06070S" target="_blank" >GA23-06070S: Fundamental research on designing of CMOS fractional-order elements</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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