The Unified Approach to Processor Testing

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F99%3A43801081" target="_blank" >RIV/00216305:26220/99:43801081 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

The Unified Approach to Processor Testing

Original language description

The focus is concentrated on different design for testability approaches being used on current processors as full scan, partial scan, standard boundary scan, and so on. An unified approach to processor testing is being proposed, combining several optimised DFT techniques, formal verification and system-level testing.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

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Project

<a href="/en/project/GA102%2F98%2F1463" target="_blank" >GA102/98/1463: Methodology and tools for digital circuits testability analysis</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

1999

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

CE&I, Sci. Conf., Kosice-Herlany, Slovakia

ISBN

80-88922-05-4

ISSN

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e-ISSN

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Number of pages

4

Pages from-to

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Publisher name

Technical University Kosice

Place of publication

Kosice-Herlany, Slovakia

Event location

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Event date

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Type of event by nationality

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UT code for WoS article

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