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Imaging Algorithm Speedup Using Co-Design

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F01%3APU28732" target="_blank" >RIV/00216305:26230/01:PU28732 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Imaging Algorithm Speedup Using Co-Design

  • Original language description

    The contribution shows a possibility to speed up image processing algorithms using a suitable combination of DSP and FPGA and also demonstrates methods to distribute the computational tasks between the DSP and FPGA.

  • Czech name

    Urychlení algoritmů rastrového obrazu pomocí co-designu

  • Czech description

    Příspěvek ukazuje možnosti urychlení algoritmů zpracování obrazu pomocí vhodné kombinace DSP a FPGA a také demonstrují metody distribude výpočetních úloh mezi DSP a FPGA.

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2001

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Summaries Volume Process Control 01

  • ISBN

    80-227-1542-5

  • ISSN

  • e-ISSN

  • Number of pages

    2

  • Pages from-to

    96-97

  • Publisher name

    Faculty of Electrical Engineering and Informatics, University of Technology Košice

  • Place of publication

    Štrbské Pleso

  • Event location

    Štrbské Pleso

  • Event date

    Jun 11, 2001

  • Type of event by nationality

    EUR - Evropská akce

  • UT code for WoS article