Vector Field Calculations on a Special Hardware Architecture

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F02%3APU36243" target="_blank" >RIV/00216305:26230/02:PU36243 - isvavai.cz</a>

Result on the web

—

DOI - Digital Object Identifier

—

Result language

angličtina

Original language name

Vector Field Calculations on a Special Hardware Architecture

Original language description

The paper proposes several methods of storing a huge array of 3D vectors in the memory of a hardware acceleration unit based on FPGA/DSP. This architecture offers effective single-bit access, and therefore proves to be more flexible in some cases, comparing to the architectures commonly used.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

—

Project

<a href="/en/project/GA102%2F02%2F0507" target="_blank" >GA102/02/0507: Computer graphics algorithms with FPGA support</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2002

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

East-West-Vision 2002 Proceedings

ISBN

3-85403-163

ISSN

—

e-ISSN

—

Number of pages

2

Pages from-to

263-264

Publisher name

TU Vienna

Place of publication

Graz

Event location

Graz

Event date

Sep 12, 2002

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

—