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Towards Evolvable IP Cores for FPGAs

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F03%3APU42538" target="_blank" >RIV/00216305:26230/03:PU42538 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    angličtina

  • Original language name

    Towards Evolvable IP Cores for FPGAs

  • Original language description

    The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectual Property) cores. The cores should be reused in the same way as ordinary IP cores are reused. In contrast to the conventional cores, the evolvable cores are able to perform autonomous evolution of their internal circuits. The cores should be available in the form of HDL source code, i.e. they should be synthesizable into any rreconfigurable device of a sufficient capacity. The approach is based on implementation of a virtual reconfigurable circuit and a genetic unit in an ordinary FPGA. In the presented case study an adaptive image filter is designed, implemented and synthesized. The proposed idea of evolvable IP core could open the way towards defining a business model for evolvable hardware.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GP102%2F03%2FP004" target="_blank" >GP102/03/P004: Evolvable hardware based applications design methods</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2003

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware

  • ISBN

    0-7695-1977-6

  • ISSN

  • e-ISSN

  • Number of pages

    10

  • Pages from-to

    145-154

  • Publisher name

    IEEE Computer Society Press

  • Place of publication

    Los Alamitos

  • Event location

    Chicago

  • Event date

    Jul 9, 2003

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article