Visualizing formal specifications using diagrams
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F03%3APU42620" target="_blank" >RIV/00216305:26230/03:PU42620 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Visualizing formal specifications using diagrams
Original language description
Although the verification process of formal models represent a long-time procedure, it is applied on more and more systems because finding and eliminating of consequent error stands for high costs. This contribution develops a front-end interface for system developers which provides automatically generation of system’s formal models utilizing the algebra of Communicating Sequential Processes. The discussed tool stem from UML composite states diagrams and utilizes behavioral diagrams to specify thee systems. The paper includes the used subset of CSP and the developed technique for automated model specification.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2003
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
11. International Conference on Software, Telecommunications & Computer Networks
ISBN
953-6114-64-X
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
165-169
Publisher name
Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture , University of Split
Place of publication
Split
Event location
Split
Event date
Oct 7, 2003
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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