VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F05%3APU55722" target="_blank" >RIV/00216305:26230/05:PU55722 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements
Original language description
The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematiical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model.
Czech name
VIRTA: Analýza a zlepšení testovatelnosti založená na virtuálních portech
Czech description
Článek se zabývá analýzou datové cesty číslicového obvodu na úrovni meziregistrových přenosů a využitím jejích výsledků ve vybraných oblastech diagnostiky číslicových systémů. Metoda je založena na tzv. virtuálních portech, konstrukci dvojice speciálníchorientovaných grafů (graf datového toku testovacích vzorků, graf datového toku odezev) a jejich analýze.
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2005
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
ISBN
963-9364-48-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
190-193
Publisher name
University of West Hungary
Place of publication
Sopron
Event location
Sopron
Event date
Apr 13, 2005
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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