Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F05%3APU56466" target="_blank" >RIV/00216305:26230/05:PU56466 - isvavai.cz</a>

Result on the web

—

DOI - Digital Object Identifier

—

Result language

angličtina

Original language name

Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs

Original language description

A specialized architecture was developed and evaluated to evolve relatively<br>large sorting networks in an ordinary FPGA. Genetic unit and fitness function are also implemented on the same FPGA. We evolved sorting networks up to N=28. The evolution of the largest sorting networks requires 10 hours in FPGA running at 100 MHz. The experiments were performed using COMBO6 card.

Czech name

—

Czech description

—

Type

D - Article in proceedings

CEP classification

JC - Computer hardware and software

OECD FORD branch

—

Project

<a href="/en/project/GP102%2F03%2FP004" target="_blank" >GP102/03/P004: Evolvable hardware based applications design methods</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2005

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Evolvable Systems: From Biology to Hardware

ISBN

978-3-540-28736-0

ISSN

—

e-ISSN

—

Number of pages

10

Pages from-to

—

Publisher name

Springer Verlag

Place of publication

Berlin

Event location

Barcelona

Event date

Sep 12, 2005

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

—