Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F07%3APU70784" target="_blank" >RIV/00216305:26230/07:PU70784 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
Original language description
TBD
Czech name
Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
Czech description
TBD
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F06%2F0599" target="_blank" >GA102/06/0599: Methods of polymorphic digital circuit design</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2007
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
ISBN
1-4244-1161-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
243-246
Publisher name
IEEE Computer Society
Place of publication
Gliwice
Event location
Krakow
Event date
Apr 11, 2007
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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