Intrusion Detection System Intended for Multigigabit Networks

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F07%3APU70839" target="_blank" >RIV/00216305:26230/07:PU70839 - isvavai.cz</a>
Alternative codes found
RIV/63839172:_____/07:00000640
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Intrusion Detection System Intended for Multigigabit Networks
Original language description
Network intrusion detection systems (IDS) are becoming an important tool for securing critical information and infrastructure. Current software-based IDS often fails to keep up with high-speed network links so a hardware based IDS is requested. This paper deals with design and implementation of complete hardware accelerated IDS solution based on Field-Programmable Gate Array (FPGA). Core generator for automatic mapping of IDS rules to FPGA logic was designed to assure fast packet classification and highspeed pattern matching. Proposed architecture has been evaluated on a COMBO6X card with FPGA Virtex-II Pro. Using COMBO6X card theoretical throughput 6.4~Gbps was achieved for all Snort rules. The designed system can be configured by rules described inSnort format using web interface.
Czech name
Systém pro detekci narušení počítačové sítě určeny pro multigigabitové sítě
Czech description
Článek popisuje architekturu sondy Traffic Scanner, které slouží pro detekci podezřelého provozu na síti.

Publication year
2007
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems
ISBN
1-4244-1161-0
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
361-364
Publisher name
IEEE Computer Society
Place of publication
Krakow
Event location
Krakow
Event date
Apr 11, 2007
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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