Implementation of Combinational and Sequential Functions in Embedded Firmware
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F07%3APU70847" target="_blank" >RIV/00216305:26230/07:PU70847 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Implementation of Combinational and Sequential Functions in Embedded Firmware
Original language description
<i>The paper addresses firmware implementation of multiple-output combinational and sequential Boolean functions based on cascades of Look-Up Tables (LUTs). A LUT cascade is described as a means of compact representation of a large class of Boolean functions, which reduces their evaluation to multiple indirect memory accesses. A LUT-oriented decom-position technique is illustrated on several examples. A specialized micro-engine is proposed for sequential processing of LUT cascades by means of multi-waybranching. The presented method provides high performance micro-programmed control for embedded applications.</i>
Czech name
Implementation of Combinational and Sequential Functions in Embedded Firmware
Czech description
<i>The paper addresses firmware implementation of multiple-output combinational and sequential Boolean functions based on cascades of Look-Up Tables (LUTs). A LUT cascade is described as a means of compact representation of a large class of Boolean functions, which reduces their evaluation to multiple indirect memory accesses. A LUT-oriented decom-position technique is illustrated on several examples. A specialized micro-engine is proposed for sequential processing of LUT cascades by means of multi-waybranching. The presented method provides high performance micro-programmed control for embedded applications.</i>
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F07%2F0850" target="_blank" >GA102/07/0850: Design and hardware implementation of a patent-invention machine</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2007
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2007 International Conference on Intelligent Pervasive Computing (IPC-07)
ISBN
978-0-7695-3006-2
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
80-85
Publisher name
IEEE Computer Society
Place of publication
Los Alamitos, California
Event location
Jeju Island
Event date
Oct 11, 2007
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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