Towards Automatic Design of Competitive Image Filters in FPGAs
Result description
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the salt and pepper noise of high intensity. An evolutionary algorithm (EA) is utilized to find a set of image filters which can be employed in abank of image filters.
The main advantage of this approach is that the bank of evolutionary designed filters requires four times less resources on a chip in comparison with the adaptive median filter while the
visual quality of filtering is preserved. The proposed solution also exhibits a very good behavior for the impulse bursts noise.
In order to design image filters in reasonable time, an FPGA-based evolutionary platform is
utilized. The proposed platform is based on the implementation
of a search algorithm in the PowerPC processor which is available in Xilinx
Virtex II Pro and newer FPGAs.
As the search algorithm as well as the evaluation of candidate solution runs in FPGA,
the evolutionary design o
Keywords
The result's identifiers
Result code in IS VaVaI
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Towards Automatic Design of Competitive Image Filters in FPGAs
Original language description
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the salt and pepper noise of high intensity. An evolutionary algorithm (EA) is utilized to find a set of image filters which can be employed in abank of image filters.
The main advantage of this approach is that the bank of evolutionary designed filters requires four times less resources on a chip in comparison with the adaptive median filter while the
visual quality of filtering is preserved. The proposed solution also exhibits a very good behavior for the impulse bursts noise.
In order to design image filters in reasonable time, an FPGA-based evolutionary platform is
utilized. The proposed platform is based on the implementation
of a search algorithm in the PowerPC processor which is available in Xilinx
Virtex II Pro and newer FPGAs.
As the search algorithm as well as the evaluation of candidate solution runs in FPGA,
the evolutionary design oCzech name
Automatizovaný návrh filtrů v FPGA
Czech description
Článek prezentuje nový přístup k FPGA implementaci obrazových filtrů využívající evoluční design.
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2008
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of Junior Scientist Conference 2008
ISBN
978-3-200-01612-5
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
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Publisher name
Technical University Wien
Place of publication
Vienna
Event location
Vídeň
Event date
Nov 16, 2008
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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Result type
D - Article in proceedings
CEP
JC - Computer hardware and software
Year of implementation
2008