Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU82613" target="_blank" >RIV/00216305:26230/09:PU82613 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming
Original language description
Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian Genetic Programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits of variable input size.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
<a href="/en/project/GA102%2F06%2F0599" target="_blank" >GA102/06/0599: Methods of polymorphic digital circuit design</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proc. of 2009 IEEE Congress on Evolutionary Computation
ISBN
978-1-4244-2958-5
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
—
Publisher name
IEEE Computational Intelligence Society
Place of publication
NA
Event location
Trondheim
Event date
May 18, 2009
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—