Usage of Decompilation in Processor Architecture Modeling

Result code in IS VaVaI
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Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Usage of Decompilation in Processor Architecture Modeling
Original language description
This paper explains concept of generic decompiler and its use in processor architecture modeling. Generic decompiler is a tool that can recompile any binary form of program to a chosen high level language representation. Output must be functionally equivalent to the input. Process of decompilation is highly dependent on the processor architecture. This problem is solvable by a special language for description of architecture and instruction semantic. Generic decompiler will be the main part of the planned tool - generic debugger. Special case of usage of such a tool is debugging optimized code for VLIW architectures, due to their complexity. The whole concept will be implemented in practice in project Lissom (FIT BUT). The Lissom project is focused onhardware/software co-design. Generic debugger will be a part of automatically generated tool-set.<br>
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2009
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of XXXIth International Autumn Colloquium Advanced Simulation of Systems
ISBN
978-80-86840-47-5
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
NEUVEDEN
Place of publication
Ostrava
Event location
Olomouc
Event date
Oct 20, 2009
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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