Instruction Selection Patterns Extraction from Architecture Specification Language ISAC
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89539" target="_blank" >RIV/00216305:26230/10:PU89539 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
Instruction Selection Patterns Extraction from Architecture Specification Language ISAC
Original language description
This paper deals with retargetable compiler generation. After a short introduction to application specific instruction set processor design, ISAC architecture description language is briefly described.<br>In the second part of this paper, algorithm thattransforms ISAC architecture model to a model usable for compiler backend generation is described. A tool that performs this translation was implemented and tested on MIPS and ARM architecture models. Compiler backend generation from the compiler generation model is still work-in-progress and is not presented here.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 16th Conference Student EEICT 2010 Volume 5
ISBN
978-80-214-4080-7
ISSN
—
e-ISSN
—
Number of pages
5
Pages from-to
—
Publisher name
Faculty of Information Technology BUT
Place of publication
Brno
Event location
FEKT VUT v Brně
Event date
Apr 29, 2010
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
—