Fast Translated Simulation of ASIPs

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU89650" target="_blank" >RIV/00216305:26230/10:PU89650 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Fast Translated Simulation of ASIPs
Original language description
Application-specific instruction set processors are the core of nowadays embedded systems. Therefore, the designers need to have powerful tools for the processor design. The tools should be generated automatically based on a processor description. One ofthe most important tools is the simulator. It is used during a testing phase of the processor design and during target software development. The key feature of the simulator is its speed. The concept of a special simulation type - translated simulation- is presented in this paper. This simulation exploits information from a target C compiler. Both the simulator and the C compiler are generated based on the processor description in an architecture description language ISAC. Experimental results of thisconcept show very good simulation speed and fast generation of the simulator.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
ISBN
978-80-87342-10-7
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
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Publisher name
Masaryk University
Place of publication
Brno
Event location
Mikulov
Event date
Oct 22, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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