Verification of Asynchronous and Parametrized Hardware Designs

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F10%3APU90556" target="_blank" >RIV/00216305:26230/10:PU90556 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Verification of Asynchronous and Parametrized Hardware Designs
Original language description
We introduce two original approaches to formal verification of hardware designs. In particular, we aim at model checking of circuits with multiple clocks and verification of parametrized hardware designs. Considering the former contribution, we introducefour methods which we use for modelling the clock domain crossing of a circuit. Models derived in such a way can then be model checked as usual while possible problems stemming from the synchronization  within a circuit are implicitly covered. Fourproposed ways of modelling a data transfer differ in their precision and the incurred verification cost. In the latter contribution, our proposed approach of verification is based on a translation of parametrized hardware designs to counter automata andon exploiting the recent advances achieved in the area of their automated formal verification. A parametrized hardware design translated to a counter automaton can be verified for all possible values of parameters at once.
Czech name
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Czech description
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Project
<a href="/en/project/GAP103%2F10%2F0306" target="_blank" >GAP103/10/0306: Static and Dynamic Verification of Programs with Advanced Features of Concurrency and Unboundedness</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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