On the cascade realization of sparse logic functions
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96015" target="_blank" >RIV/00216305:26230/11:PU96015 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
On the cascade realization of sparse logic functions
Original language description
Representation of multiple-output logic functions by Multi-Terminal Binary Decision Diagrams (MTBDDs) is studied for the useful class of sparse logic functions specified by the number of true min-terms. This paper derives upper bounds on the MTBDD width,which determine the size of look-up tables (LUTs) needed for hardware realization of these functions in FPGA logic synthesis. The obtained bounds are generalization of similar known bounds for single-output logic functions. Finally a procedure how to find the optimum mapping of MTBDD to a LUT cascade is presented and illustrated on a set of benchmarks.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GAP103%2F10%2F1517" target="_blank" >GAP103/10/1517: Natural Computing on Unconventional Platforms</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Euromicro Proceedings
ISBN
978-0-7695-4494-6
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
21-28
Publisher name
IEEE Computer Society
Place of publication
Oulu
Event location
Oulu
Event date
Aug 31, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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