Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F11%3APU96159" target="_blank" >RIV/00216305:26230/11:PU96159 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity
Original language description
Intrusion Detection Systems have to match large sets of regular expressions to detect malicious traffic on multi-gigabit networks. Many algorithms and architectures have been proposed to accelerate pattern matching, but formal methods for reduction of Nondeterministic finite automata have not been used yet. We propose to use reduction of automata by similarity to match larger set of regular expressions in FPGA. Proposed reduction is able to decrease the number of states by more than 32% and the amount of transitions by more than 31%. The amount of look-up tables is reduced by more than 15% and the amount of flip-flops by more than 34%.
Czech name
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Czech description
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Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
ISBN
978-1-4244-9753-9
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
401-402
Publisher name
IEEE Computer Society
Place of publication
Cottbus
Event location
Cottbus
Event date
Apr 13, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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